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  1. T. Park, H.Jeong, S. Park, S. Hong, S. Seo, S. Park, S. Choi
    The Effect of Schottky Barrier Modulation on Conduction and Failure Mechanisms of an Ag/WOx/p-Si Based Memeristor
    Journal of Applied Physics, Accepted (2023)

  2. G. Kim, S. Son, H. Song, J. Jeon, J. Lee, W. Cheong, S. Choi, K. Kim
    Retention Secured Nonlinear and Self-Rectifying Analog Charge Trap Memristor for Energy-Efficient Neuromorphic Hardware
    Advanced Science, 10, 2205654 (2023)

  3. S. Seo*, B.Kim*, D. Kim*, S. Park*, T.R. Kim, J.Park, H.Jeong, S. Park, T. Park, H.Shin, M.Kim, Y. Choi, S. Choi
    The gate injection-based field-effect synapse transistor with linear conductance update for online training
    Nature Communications, 13, 6431 (2022)
    • (Press)       Introduced to various media (see News for details)
  4. S. Park*, H. Jeong*, J. Park*, J.Bae, S. Choi
    Experimental demonstration of highly reliable dynamic memristor for artificial neuron and neuromorphic computing
    Nature Communications, 13, 2888 (2022)
    • (Highlight) Selected as Featured Image In Nature Communications Homepage
    • (Highlight) Featured In Nature Communications Editors' Highlights
    • (Award)      Selected for the KAIST 2022 Fall Breakthrough Research of the College of Engineering
    • (Press)       Introduced to various media (see News for details)
  5. S. Choi*, S. Park*, S. Seo, S. Choi
    Reliable multilevel memristive neuromorphic devices based on amorphous matrix via quasi-1D filament confinement and buffer layer
    Science Advances, 8, 3 (2022)
    • (Press) Introduced to various media (see News for details)
  6. M. Kim, J. Kim, G. Yun, J. Yu, J. Han, J. Lee, S, Seo, S. Choi, Y. Choi
    An Overturned Charge Injection Synaptic Transistor With a Floating-Gate for Neuromorphic Hardware Computing
    IEEE Electron Device Letters, 43, 9 (2022)

  7. S. Hu, J. Kang, T. Kim, S. Lee, J. Park, I. Kim, J. Kim, J. Kwak, J. Park, G. Kim. S. Choi†, Y. Jeong†
    SPICE study of STDP characteristics in a drift and diffusive memristor-based synapse for neuromorphic computing
    IEEE Access, 10, 6381-6392 (2022) (Co-corresponding author)

  8. Y. Jeong, H. Lee, J. Park, S. Lee, H. Jin, S. Park, H. Cho, S. Hong, T. Kim, K. Kim, S. Choi, S. Im
    Engineering MoSe2/MoS2 Heterojunction Traps in 2D Transistors for Multilevel Memory, Multiscale Display, and Synaptic Functions
    NPJ 2D Materials and Applications, 6 (23), (2022)

  9. J. Jeong, S. Kim, J. Kim, D. Geum, D. Kim, E. Jo, H. Jeong, J. Park, J. Jang, S. Choi, I. Kwon, S. Kim
    Heterogeneous and Monolithic 3D Integration of III–V-Based Radio Frequency Devices on Si CMOS Circuits
    ACS Nano (2022)

  10. J. Park, Y. Lee, H. Jeong, S. Choi
    Neural Network Physically Unclonable Function: A Trainable Physically Unclonable Function System with Unassailability against Deep Learning Attacks Using Memristor Array
    Advanced Intelligent Systems 3 (11) , 210011 (2021)
    • ​(Cover) Selected as the front cover.​
  11. S. Park, Y. Jeong, H. Jin, J. Park, H. Jang, S. Lee, W. Huh, H. Cho, H. G. Shin, K. Kim, C. Lee, S. Choi, S. Im
    Nonvolatile and Neuromorphic Memory Devices Using Interfacial Traps in Two Dimensional WSe2/MoTe2 Stack Channel
    ACS Nano, 14(9) (2020)

  12. J. Cha, S.Y. Yang, J. Oh, S. Choi, S. Park, B.C. Jang, W.Ahn, S. Choi
    Conductive-Bridging Random-Access Memories for Emerging Neuromorphic Computing
    Nanoscale (2020)​

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  13. S. Tan, P. Lin, H. Yeon, S. Choi, Y. Park and J. Kim
    Perspective: Uniform Switching of Artificial Synapses for Large-Scale Neuromorphic Arrays
    APL Materials, 6, 120901 (2018)

  14. S. Choi*, S. Tan*, Z. Li, Y. Kim, C. Choi, P. Chen, H. Yeon, S. Yu and J. Kim
    SiGe Epitaxial Memory for Neuromorphic Computing with Reproducible High Performance Based on Engineered Dislocations.
    Nature Materials, 17, 335-340 (2018)
    • (News & Views) Highlighted in News & Views of Nature Materials
    • (MIT new)           Spotlighted in MIT main page, MIT news
  15. Y. Kim, S. Cruz, K. Lee, B. Alawode, C. Choi, Y. Song, J. Johnson, C. Heidelberger, W. Kong, S. Choi, K. Qiao, I. Almansouri, E. Fitzgerald, J. Kong, A. Kolpak, J. Hwang, and J. Kim
    Remote epitaxy through graphene for two-dimensional material based layer transfer
    Nature, 544, 340-343 (2017)​
    • ​(Cover) Selected as the front cover.​
  16. S. Choi*, J. Shin*, J. Lee and W. Lu
    Experimental Demonstration of Feature Extraction and Dimensionality Reduction using Memristor Networks
    Nano Letters, 17, 3113-3118 (2017)
    • (Highlight) Highlighted in Nature Nanotechnology.
  17. S. Choi*, P. Sheridan*, and W. D. Lu
    Data Clustering using Memristor Networks
    Scientific Reports, 5, 10492. (2015)

  18. S. Kim, C. Du, P. Sheridan, W. Ma, S. Choi, and W. D. Lu
    Experimental Demonstration of a Second-Order Memristor and Its Ability to Biorealistically Implement Synaptic Plasticity
    Nano Letters,15(3), 2203-2211. (2015)

  19. S. Kim*, S. Choi*, J. Lee, and W. Lu
    Tuning Resistive Switching Characteristics of Tantalum Oxide Memristors through Si Doping
    ACS Nano, 8(10), 10262-10269. (2014)

  20. Y. Yang, P. Gao, L. Li, X. Pan, S. Tappertzhofen, S.Choi, R. Waser, I. Valov, and W. Lu
    Electrochemical Dynamics of Nanoscale Metallic Inclusions in Dielectrics
    Nature Communications 5, 4232. (2014)

  21. S. Choi, J. Lee, and W. Lu
    Retention Failure Analysis of Metal-Oxide Based Resistive Memory
    Applied Physics Letters, 105, 113510. (2014)

  22. S. Kim, S. Choi, and W. Lu
    Comprehensive Physical Model of Dynamic Resistive Switching in an Oxide Memristor
    ACS Nano, 8(3), 2369-2376. (2014)

  23. S. Choi, Y. Yang, and W. Lu
    Random Telegraph Noise and Resistance Switching Analysis of Oxide Based Resistive Memory
    Nanoscale, 6, 400-404. (2014)

  24. Y. Yang, S. Choi, and W. Lu
    Oxide Heterostructure Resistive Memory
    Nano Letters, 13, 2908 (2013)

  25. S. Gaba, P. Sheridan, J. Jiantao, S. Choi, and W. Lu
    Stochastic Memristive Devices for Computing and Neuromorphic Applications
    Nanoscale, 5, 5872 (2013)

  26. T. Moon, L. Chen, S. Choi, C. Kim, and W. Lu
    Efficient Si Nanowire Array Transfer via Bi-Layer Structure Formation Through Metal-Assisted Chemical Etching
    Advanced Functional Materials doi: 10.1002/adfm.201303180. (2013)

  27. S. Gaba, S. Choi, P. Sheridan, T. Chang, Y. Yang, and W. Lu
    Improvement of RRAM Device Performance Through On-Chip Resistors
    Mater. Res. Soc. Symp. Proc. 1430, 177 (2012).
* Equally contributed.
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